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Abstract Piezoelectric resonators are becoming attractive alternatives to conventional magnetics in DC-DC converters due to their favorable scaling and manufacturing properties. However, the efficiency and current handling capabilities of baseline piezoelectric resonator-based DC-DC converters degrade at higher voltage conversion ratios due to charge utilization limitations imposed by topological operation. Here we present an Always-Multi-Path Embedded Flying Capacitor Piezoelectric Resonator-based DC-DC converter that uses flying capacitors to add both hybrid multi-path output power delivery features and to reduce the internal charge redistribution losses within the piezoelectric resonator. Specifically, the proposed integrated circuit modifies the optimal voltage conversion of the piezo network from 2:1 to 3:1 while adding a switched-capacitor output network that enables multi-path operation at all times, resulting in a net optimal voltage conversion ratio of 9:1 for the converter, with 4x improved output current. Fabricated in a 180 nm high-voltage CMOS process, the developed chip achieves a peak efficiency of 96.2% at a 48-to-4.8 V conversion ratio. 

Intracortical brain computer interfaces (iBCIs) utilizing extracellular recordings mainly employ in vivo signal processing application-specific integrated circuits (ASICs) to detect action potentials (spikes). Conventionally, “brain-switches” based on spiking activity have been employed to realize asynchronous (self-paced) iBCIs, estimating when the user involves in the underlying BCI task. Several studies have demonstrated that local field potentials (LFPs) can effectively replace action potentials, drastically reducing the power consumption and processing requirements of in vivo ASICs. This article presents the first LFP-based brain-switch design and implementation using gated recurrent neural networks (RNNs). Compared to the previously reported brain-switches, our design requires no exhaustive learning phase for the estimation of optimal recording channels or frequency band selection, making it more applicable to practical asynchronous iBCIs. The synthesized ASIC of the designed in vivo LFP-based feature extraction unit, in a standard 180-nm CMOS process, occupies only 0.09 mm^2 of silicon area, and the post place-and-route synthesis results indicate that it consumes 91.87 nW of power while operating at 2 kHz. Compared to the previously published ASICs, the proposed LFP-based brain-switch consumes the least power for in vivo digital signal processing and achieves comparable state estimation performance to that of spike-based brain-switches. 

Conventional in vivo neural signal processing involves extracting spiking activity within the recorded signals from an ensemble of neurons and transmitting only spike counts over an adequate interval. However, for brain-computer interface (BCI) applications utilizing continuous local field potentials (LFPs) for cognitive decoding, the volume of neural data to be transmitted to a computer imposes relatively high data rate requirements. This is particularly true for BCIs employing high-density intracortical recordings with hundreds or thousands of electrodes. This article introduces the first autoencoder-based compression digital circuit for the efficient transmission of LFP neural signals. Various algorithmic and architectural-level optimizations are implemented to significantly reduce the computational complexity and memory requirements of the designed in vivo compression circuit. This circuit employs an autoencoder-based neural network, providing a robust signal reconstruction. The application-specific integrated circuit (ASIC) of the in vivo compression logic occupies the smallest silicon area and consumes the lowest power among the reported state-of-the-art compression ASICs. Additionally, it offers a higher compression rate and a superior signal-to-noise and distortion ratio.